Advanced VLSI Design, 6 HP

Course Information

• General
• Staff
• Laboratory Exercises
  
• Examination
  
• Schedule
  

NEWS:
100311: This course web site will no longer be updated after the exam period in April. After the exam, check TSEK37 for related course information

General

• Aim:
  This course is intended to give a detailed knowledge and experience in design of advanced VLSI circuits and chips in today's and future nano-scale CMOS technologies. Major VLSI design challenges will be studied, followed by careful treatment of several versatile analog, digital, and mixed analog-digital circuit building blocks frequently utilized in VLSI chips.
• Course Code:
  TSEK36 Advanced VLSI Design / Avancerad VLSI-konstruktion, Y4, D4 and IT4, 6 hp
• Prerequisites:
  TSTE86 Digital Integrated Circuits.
• Supplementary courses:
  VLSI Design Project, TSEK06, where students follow the entire VLSI design-flow and make 'Real' chips in a standard CMOS process.
• Organization:
  This course comprises 13 lectures, 6 tutorials, and 12 hours laboratory exercises. The 6 tutorials support the course by detailed analysis of some problem examples, and the 12 hours laboratory exercises allows students to learn circuit design, simulations, and evaluation techniques utilizing professional CAD tools and standard CMOS process technology models and parameters.
• Background and motivation:
  Today's and future advanced VLSI chips can comfortably include over one billion of transistors in a single piece of silicon with an area of a few square millimeters! Obviously, these transistors are not just there randomly, but each device is carefully designed and positioned to do its job, and to interact with other devices and circuits which might be in the neighborhood or sometimes in the far end of the chip! Despite 6-7 electrically isolated metal layers available on-chip, it's not so hard to imagine what a nightmare is to lay out these billion of devices and to route all the interconnections between them!
  This might sound cool and challenging enough, but we haven't even scratched the surface yet! It's just the beginning of the story! Even if you have completed the entire layout correctly, still, who knows that the chip will really work? What about all those tough power and performance specifications which must be met in the presence of serious and increasingly large process variations? How do you know that the real chip will operate as you expect. Did you model everything correctly across all process corners? Did you simulate everything correctly? Did you take into account all noise sources? Did you use a correct circuit topology with sufficient robustness against potential noise and signal timing uncertainties? Did you follow all the manufacturing requirements for product reliability and life time? Is that really a high-yield design, where at least over 90% of the chips will work and can be shipped out to customer? ....OR you are just about to fail A Multi-Million Dollar project?
• Course contents:
  The course will focus on the following topics:
  1- Overview of advanced CMOS process technologies.
  2- Modeling of MOS transistors and passive elements for analog and digital circuits.
  3- Circuit analysis as well as design and simulation strategies required to evaluate analog and digital CMOS integrated circuits. As a representative benchmark, different amplifier stages and other basic circuit building blocks will be studied. The circuit analyses will take into account non-ideal effects such as noise and potential variations in process parameters, terminals voltages, and operating temperature.
  4- On-chip interconnects design and I/O interface circuits. This includes studies on interconnects delay models for high-speed data transmission as well as power and performance analysis of on-chip buses including driver/receiver circuits.
  5- On-chip timing and synchronization techniques, including detailed studies on clock generators, clock distribution networks, and clocking elements such as latches and flip-flops. Also, major clock- and data-recovery circuits such as phase- and delay-locked-loops will be discussed.
  6- Analysis of on-chip power consumption, low power circuit techniques, transistor leakage currents, and leakage current reduction techniques for both active and standby operating modes.
  7- On-chip power delivery and management, including power distribution and power delivery techniques.
  8- Overview of chip manufacturing requirements such as product yield and product reliability, as well as chip testing methodologies.
  
• More information for students who are planning their future courses:
  "VLSI" refers to Very Large Scale Integrated circuits (chips that can today include over billions of transistors in a single and small piece of silicon). For example microprocessors in PC's and other computers are VLSI chips. The department of electrical engineering (ISY) provides a world class VLSI education package including 4 courses starting with (i) the introductory course, Digital Integrated Circuits, TSTE86, (ii) the Advanced VLSI course, TSEK36 (this course), and (iii) the 'ultimate' and perhaps the most expensive course in LiTH, "VLSI Chip Design Project course", TSEK06, where students follow the entire VLSI design flow and make "Real" chips in a standard CMOS process. The chips can then be measured in a short course, "Evaluation of an Integrated Circuit", TSEK11.


• Course literature:
  1- Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 1st Edition McGraw-Hill Higher Education, ISBN 9780071188395
  2- Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits", Prentice Hall, Second Edition (International edition), ISBN 0-13-120764-4 (The same book used in the introductory course, TSTE86, Digital Integrated Circuits).
  
• Examination:
  TEN1 Written Exam. 4.5 ECTS credits (3p Swedish)
  LAB1 Laboratory work. 1.5 ECTS credits (1p Swedish)
• www:
  On the current home page, news will be provided as the course progresses -- especially you should keep track on the schedule. The home page contains links to a number of pdf documents that you can download:
• Staff
  
• Examiner:
  Atila Alvandpour, Professor
  Electronic Devices, Dept. of Electrical Engineering (ISY)
  Office 229:206, B-building
  Tel: 285818
  E-mail: atila@isy.liu.se

Behzad Mesgarzadeh, Ass. Prof.
Electronic Devices, Dept. of Electrical Engineering (ISY)
Office: 229:214, B-building
Tel: 285719
E-mail: behzad@isy.liu.se


• Teaching Assistants:
  Jonas Fritzin, PhD student, Head Teaching Assistant
  Electronic Devices, Dept. of Electrical Engineering (ISY)
  Office 229:208, B building
  Tel: 282671
  E-mail: fritzin@isy.liu.se
  
  Dai Zhang, PhD student
  Electronic Devices, Dept. of Electrical Engineering (ISY)
  Office: 229:198, B-building
  Tel: 282703
  E-mail: dai@isy.liu.se

Ali Fazli, PhD student
Electronic Devices, Dept. of Electrical Engineering (ISY)
Office: 229:212, B-building
Tel: 282254
E-mail: ali@isy.liu.se

LABORATORY EXERCISES

There are one laboratory exercise in this course; AnalogLab, which is divided into 3 parts and 3 lab occasions. No registration is required! Carefully prepare the lab! Do not show up un-prepared!!!

Course Labs:

• AnalogLab

TUTORIALS

Before each tutorial (as the course proceeds) you will be able to download supplementary material such as answers and hints to exercises that will be treated.

If you want to print all tutorials at once, they are all collected in this file.

Tutorial 1:

• Exercises for tutorial 1
• Answers for tutorial 1

Tutorial 2:

• Exercises for tutorial 2
• Answers for tutorial 2

Tutorial 3:

• Exercises for tutorial 3
• Answers for tutorial 3

Tutorial 4:

• Exercises for tutorial 4
• Answers for tutorial 4

Tutorial 5:

• Exercises for tutorial 5
• Answers for tutorial 5

Tutorial 6:

• Exercises for tutorial 6
• Answers for tutorial 6

Tutorial 7:

• Exercises for tutorial 7
• Answers for tutorial 7

Tutorial 8:

• Exercises for tutorial 8
• Answers for tutorial 8

Extra exercises:

• Extra exercises
• Answers for extra exercises

EXAMINATION

Examination 2007-12-20:

• Examination 2007-12-20
• Solutions to examination 2007-12-20

Examination 2008-12-19:

• Examination 2008-12-19
• Solutions to examination 2008-12-19

Examination 2009-12-21:

• Examination 2009-12-21
• Solutions to examination 2009-12-21

SCHEDULE

• Schedule TSEK36 2009 (PDF)

• FÖ = Lecture, LE = Exercise, LA = Lab

Week 44, 2009			Kurs	Moment	Studentgrp	Lärare	Lokal	Anmärkning
Mon	26 oct	13:00-15:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	A1
Wed	28 oct	10:00-12:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C3
Fri	30 oct	15:00-17:00	TSEK36	LE	SOC1, COE1	Dai Zhang	U10
		15:00-17:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	S41
Week 45, 2009
Mon	2 nov	13:00-15:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C3
Wed	4 nov	10:00-12:00	TSEK36	LE	SOC1, COE1	Ali Fazli	BL32
		10:00-12:00	TSEK36	LE	SOC1, COE1	Dai Zhang	G32
Fri	6 nov	15:00-17:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C4
Week 46, 2009
Mon	9 nov	13:00-15:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	G32
		13:00-15:00	TSEK36	LE	SOC1, COE1	Ali Fazli	U11
Wed	11 nov	10:00-12:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C4
Fri	13 nov	15:00-17:00	TSEK36	LE	SOC1, COE1	Dai Zhang	S26
		15:00-17:00	TSEK36	LE	SOC1, COE1	Ali Fazli	T2
Week 47, 2009
Mon	16 nov	13:00-15:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C2
Wed	18 nov	10:00-12:00	TSEK36	LE	SOC1, COE1	Ali Fazli	G32
		10:00-12:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	S41
Fri	20 nov	15:00-17:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C2
Week 48, 2009
Mon	23 nov	13:00-15:00	TSEK36	FÖ	SOC1, COE1	Behzad Mesgarzadeh	C4
Wed	25 nov	10:00-12:00	TSEK36	LE	SOC1, COE1	Ali Fazli	G32
		10:00-12:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	T2
		17:00-21:00	TSEK36	LA	SOC1, COE1		ASGA, EGYP, OLYM, SOUT
Fri	27 nov	15:00-17:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	C4
Week 49, 2009
Mon	30 nov	13:00-15:00	TSEK36	LE	SOC1, COE1	Ali Fazli	U11
		13:00-15:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	S41
Tue	1 dec	17:00-21:00	TSEK36	LA	SOC1, COE1		ASGA, EGYP, OLYM, SOUT
Wed	2 dec	08:00-10:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	C1
		17:00-21:00	TSEK36	LA	SOC1, COE1		ASGA, EGYP, FREJ, OLYM
Fri	4 dec	15:00-17:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	C4
Week 50, 2009
Mon	7 dec	13:00-15:00	TSEK36	LE	SOC1, COE1	Jonas Fritzin	D38
		13:00-15:00	TSEK36	LE	SOC1, COE1	Ali Fazli	S41
Wed	9 dec	10:00-12:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	C4
Fri	11 dec	15:00-17:00	TSEK36	FÖ	SOC1, COE1	Atila Alvandpour	C4