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ISY > Electronic Devices
Ceniit Research Project (10.01)
EMI Reduction by Resonant Clock Distribution Networks for Automotive Applications
Researcher: Behzad Mesgarzadeh, Ph.D.
Project Information
Objective
In today’s automotive vehicles, electromagnetic interference (EMI) from electronic circuits has become a serious concern. Automotive industry standards set regulations on the level of unwanted radiated emissions which make the electronic system design limited. In this research project, the objective is to introduce resonant clock distribution networks as a low-power alternative for today’s conventional clocking, in which the EMI performance of clocked circuits is improved significantly.
Introduction
The ever-increasing complexity and speed in today’s integrated circuits, due to aggressive technology scaling, introduce new challenges in design and fabrication of advanced VLSI circuit. In digital design, fast and sharp clock edges are utilized for synchronization purpose in large-scale chips. As an example, in microprocessors with millions of transistors, a conventional buffer-driven clock tree is typically utilized to synchronize all clocked device connected to the leaves. In such a synchronization scheme, all sharp and fast clock edges occur at the same time creating large current pulses on the power network. These fast current variations increase resulting in higher simultaneous switching noise (SSN), which is one of the important sources of electromagnetic interference (EMI) [1]. Nowadays, since in many applications (e.g., automotive vehicles) electronic circuits are playing a crucial role, without employing proper EMI reduction techniques, electromagnetic compatibility (EMC) becomes a serious liming factor.
In order to suppress SSN, one way is to distribute clock edges within a specific timeslot, as long as it is allowed by timing constraints. This helps to prevent simultaneous occurrence of clock edges. However, this technique is not directly supported by CAD tools and proper clock drivers should be utilized for implementation of this concept. Different spread spectrum clocking (SSC) techniques based on clock modulation are previously proposed [2], [3]. Another effective technique to suppress SSN is to employ on-chip and off-chip decoupling capacitors (i.e., decaps) [4]. A study on effectiveness of this technique has been presented in [5]. Although decoupling capacitors exhibit potential of SSN suppression and consequently EMI reduction, careful optimization is required to calculate the proper capacitance size. The reason is that on-chip decoupling capacitors typically occupy a large portion of active area. As mentioned earlier, fast clock edges contain large harmonic components, which increase the total radiated EMI. Due to this fact, one low-cost solution to reduce EMI is to employ a clock signal with relaxed rise and fall time (i.e., slower clock edges) [6]. Obviously, this technique creates some difficulties in management of timing budget for high-speed applications. However, in automotive applications in which typically, clock frequency does not exceed few hundreds of megahertz, this technique can be extremely efficient.
Recently, we have introduced and analyzed resonant clock distribution networks as a low-power alternative for the conventional buffer-driven clocking in state-of-the-art publications presented in international journal and conferences [7]-[9]. In this project, the objective is to investigate this clocking strategy in the context of EMI reduction. In this technique, since a sinusoidal clock is generated for the clock distribution purpose, the peak energy of higher harmonic components is suppressed significantly, and it is supposed to exhibit lower EMI radiation.
Background
In this research project, resonant clock distribution networks are investigated from two important perspectives as they are discussed in the following.
A. Clock Power Reduction
A significant fraction of the total active power consumption in microprocessors and other advanced high-speed VLSI chips is due to clocking [10], [11]. Conventional high performance clocking techniques are mature and robust. Still, they are based on a relatively rigid and traditional philosophy, which enforces a power-hungry clock distribution network, leaving almost no room for low power. Typically, in the conventional clock distribution networks, buffer stages are utilized to deliver the clock signal to different parts and sections inside the network. These buffer stages are shown to be power-hungry and inefficient components of clocking network. Due to this fact, resonant-clocking techniques have been introduced recently as low power alternatives for traditional schemes [7]-[9]. In this technique, in order to reduce the clock power, all the buffer stages are removed and the final load is directly driven by an LC tank as shown in Fig. 1. Hence, the energy resonates between an inductor and the clock load enabling charge recovery clocking. Although ideally the power efficiency of a resonant clocking scheme can approach 100%, in today’s standard CMOS technologies, the energy losses due to the parasitic resistances in the inductance and interconnect network result in considerable clock power dissipation. However, significant clock-power savings (i.e., more than 60%) can still be achieved compared to conventional clocking schemes. Such power savings have recently been reported [7]-[9].
Fig.1. A simplified model of a resonant clock distribution network.
Resonant clock distribution networks show great potential in significant power savings, however, there are still problems left to be solved to make this technique applicable in future’s microprocessors. Some of these problems, which will be investigated in this research project, are as follows: clock gating techniques, which allow the microprocessor to save power during the sleep-mode, should be investigated carefully. Since in resonant clocking an LC oscillator is responsible for clock generation, clock cannot be shut down locally. Due to this reason, new clock gating techniques should be introduced. The second problem is that a microprocessor should be tested in low frequencies. For this purpose, a low-frequency clock is applied in the test mode. However, in resonant clocking the frequency tuning range is limited by its LC oscillator making it difficult to run the microprocessor in the test mode. Another issue in design of resonant clocking is the driving capability of the LC oscillator. Since the clock load determines the oscillation frequency, connecting large capacitive loads to the oscillator decreases its driving capability and reduces the clock frequency. To solve this problem, using a multi-domain clock network can be helpful.
B. EMI Reduction
The maximum electromagnetic radiation in an electronic circuit depends on both the frequency and the current flowing in conductors. Due to this fact, the frequency spectrum of the current waveform can be considered as a proper indicator for unwanted radiated emissions. For a conventional trapezoidal clock waveform shown in Fig. 2(a), the th harmonic with rise and fall times equal to is
where is the peak-to-peak amplitude of the waveform, is the clock period, is the “high” pulse width. Fig. 2(b) shows the spectrum magnitude for a 1-MHz trapezoidal current waveform with 1-A peak-to-peak amplitude and 30-ns rise and fall time. As it is shown in this figure, for frequencies beyond , the amplitude of higher harmonics decreases with a 20 dB per decade rate up to a breaking point at frequency of MHz, and beyond this point reduction rate increase to 40 dB per decade.
(a)
(b)
Fig.2. : (a) A trapezoidal waveform and (b) its spectrum envelope.
Discussion above proves that the relaxed clock edges are helpful in reducing the unwanted radiation from digital circuits. However, practically, it is not possible to use very slow clock edges. The reason is that these kinds of clock shapes make it extremely difficult to run digital blocks with reasonable performance and within the desired timing margins. Furthermore, in none of the discussed cases, high frequency radiations are avoidable, since high frequency components cannot be eliminated completely. Considering these facts, the most efficient solution is to employ a sinusoidal current waveform in which ideally, frequency spectrum contains no higher harmonics. Due to this reason, resonant clock distribution networks can exhibit great potential of EMI reduction in associated applications.
In this project, a detail analysis of EMI reduction capability in resonant clock networks will be performed. This gives us good understanding about different circuit techniques, which can be employed in industrial applications as low-power low-EMI alternatives for today’s conventional circuitry.
Summary of Problem Formulation
Based on the foregoing discussion the main issues which should be addressed in this research project are as follows:
• Proper analysis and modeling of EMI reduction capability of resonant clock networks
• Investigation about industrial requirements introduced by EMC specially in automotive applications
• Introducing new techniques based on resonant clocking to overcome problems associated with unwantedradiations
• Solving the clock gating problem in resonant clock networks
• Increasing the frequency tuning range of the clock source in resonant clock network
• Realizing multi-domain resonant clock distribution networks [12]
Industrial Relevance
In automotive applications EMI problem is considered as a serious issue due to significant increase in number of electronic devices in today’s cars. Introducing new design methodologies will definitely have great impact on today’s car industry. On the other hand, resonant clock distribution can be considered as a revolutionary power reduction technique in future’s VLSI design. Since the speed and clock frequencies are virtually increased by parallelism in multi-core implementations, power dissipation is the main limiting factor for the future generations. From industry point of view, ST microelectronics (as an EMC-compatible circuit designer for car industry) and Intel’s Circuit Lab (as the biggest microprocessor producer) have shown interest in the development of resonant clocking. Our research group has had collaboration with Intel during the last five years and they have shown interest in financing this research partially. Furthermore, IBM has announced its new Cell Broadband-Engine Processor, which utilizes resonant clock distribution [13]. New trend to replace the conventional methodology with resonant clocking has been started and due to this fact, the research project in this application has high potential to be industrialized in near future. Based on the preceding discussion, solving the mentioned problems will definitely facilitate the process of industrializing of this technique and LIUs researchers will be pioneer in this process.
Project Plan and Goals
The main goals of the project are as follows:
• The problems mentioned at the end of Section II will be addressed in theoretical and simulation level.
• The achieved solutions will be verified experimentally by real chip implementations.
• Results achieved by experimental verifications will be published in the related international journals and conferences.
• In a three-year research period, visits to advanced circuit labs in microprocessor production companies (e.g., Intel), car and aircraft industry (e.g., Volvo, SAAB, etc.) and academic research labs will be planned.
• The main goal is to achieve international visibility in this field by introducing low-power solutions which have capability in EMI reduction for the future generations of circuits and microprocessors utilized in an industrial level.
This research project will be started by a study of potential solutions for the mentioned problems. In this phase, system and circuit simulations will be performed to evaluate the possible solutions. In the second phase of this project, a real circuit application will be implemented on silicon to test the analysis and idea itself. The third phase of this research project will be dedicated to introducing low-power circuits with low EMI, which can be utilized in automotive applications. All circuit implementations will be followed by experimental verification and measurements to evaluate the proposed solutions. Summarizing the project plan, we expect to have at least two chip implementations (design and fabrication) in advanced CMOS processes, followed by proper testing and measurements in the defined time frame for the project.
Project Visions
We expect to publish the results achieved in this project in the form of various international publications in a three-year timeframe. Furthermore, we expect to show the industrializing potential of this technique experimentally. To realize this vision, the research project requires a research team with excellent background in this area. To build this team, a combination of M.Sc. and Ph.D. students should be employed in different phases. We intend to establish a research group in a long-term perspective.
Due to the high research potential of this project, we predict to produce one Ph.D. thesis plus a few master theses to complete the project. Moreover, from financial support point of view, it is planned to apply to funding agencies in Sweden (e.g. VR, SSF, etc.), inside EU and worldwide (e.g. Intel Corporations) to cover the expenses for supporting the established research group in a long-term view.
Research Environment
This research project will be performed in the Division of Electronic Devices (EK) in Electrical Engineering Department (ISY). The research in this division covers a variety of different topics in integrated circuit design (e.g. digital circuits, data converters, RF circuits, etc.). Several Ph.D. and M.Sc. theses have been completed in this group so far in the mentioned areas. The Division of Electronic Devices has also collaboration with many industrial partners worldwide including Intel, Philips, ACREO, Ericsson, etc.
Other CENIIT Projects: Although this research project is not closely related to the current CENIIT projects, the results produced by this project can either directly or indirectly be utilized by other projects like 05.06 (Test design for computer systems with a life-time perspective).
Project Progress and Industrial Collaborations
A thorough study of on-chip EMI and noise sources has been performed so far to have a good understanding about the phenomenon. In [P9], resonant clocking has been introduced as a low EMI clock distribution technique. In this article, a simplified model has been presented to prove the EMI reduction potential in such a clocking network.
In [P6], we propose a new clocking strategy which provides higher flexibility to reduce the on-chip EMI. A complete analysis of EMI and short-circuit power dissipation is provided in this paper.
Studies and designs discussed in [P2] and [P4] are focused on reducing the simultaneous switching noise (SSN) in digital circuits which is one of the most important sources of EMI.
In [1] and [5], other aspects of clock generation have been discussed. The focus of these articles is to synthesis a low noise clock for digital and RF applications in a low-cost and efficient manner to reduce the design complexity.
Two Master’s theses have been performed targeting the problem formulated in this project ([P6] and [P7]). There are also new Master theses which we have started to investigate these problems.
A new industrial collaboration has been established with SAAB and FMV. We have got also some fund to start a project which is in line with this research project. In this project, reliability issues in design of avionics are focused. Silicon aging and also effect of unwanted radiations on avionics are investigated through this project. We have published a paper as an outcome for this industrial collaboration [P3]. There is great interest from both sides to continue this research collaboration.
Researchers
• Behzad Mesgarzadeh, Ph.D., Project leader
• Amin Ojani, Ph.D. student
• Iman Esmail Zadeh, Master student
• Sahar Kasholayat, Master student
• Golnaz Emrahimi Mehr, Master student
Publications
[P1] A. Ojani, B. Mesgarzadeh, and A. Alvandpour, "A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB", in Proc. IEEE Symp. on Circuits and Systems (ISCAS), 2012.
[P2] B. Mesgarzadeh and A. Alvandpour, "Simultanous Switching Noise Reduction by Resonant Clock Distribution Networks", Submitted, 2012.
[P3] B. Mesgarzadeh, I. Söderquist, and A. Alvandpour, "Reliability Challenges in Avionics due to Silicon Aging", in Proc. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2012.
[P4] J. Fritzin, B. Mesgarzadeh and A. Alvandpour, "A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation", Submitted, 2012.
[P5] A. Ojani, A. Bhide, B. Mesgarzadeh, and A. Alvandpour, "A Low-Power Calibration Technique in DLL-Based Frequency Synthesize for WiMedia UWB", Submitted, 2012.
[P6] I. Esmail Zadeh, "A Study and Implementation of On-Chip EMC Techniques", Master's thesis, Linköping University 2011.
[P7] S. Kashfolayat, "A Study of Clocking Techniques to Reduce Simultaneous Switching Noise (SSN) in On-Chip Applications", Master's thesis, Linköping University 2011.
[P8] B. Mesgarzadeh, I. Esmail Zadeh, and A. Alvandpour, "A Multi-Segment Clocking Scheme to Reduce On-chip EMI", in Proc. IEEE SoC Conference (SoCC), 2011.
[P9] B. Mesgarzadeh and A. Alvandpour, "EMI Reduction by Resonant Clock Distribution Networks", in Proc. IEEE Symp. on Circuits and Systems (ISCAS), pp. 977-980, 2010.
References
[1] T. Osterman, B. Deutschman, and C. Bacher, “Influence of the power supply on the radiated electromagnetic emission of integrated circuits,” Microelectronics Journal, vol. 35, pp. 525–530, June 2004.
[2] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in Proc. Intl. Symp. Electromagnetic Compatibility, pp. 227–231, 1994.
[3] J. Kim, D. G. Kam, P. J. Jun, and J. Kim, “Spread spectrum clock generator with delay cell array to reduce electromagnetic interference,” IEEE Trans. On Electromagnetic Compatibility, vol. 47, pp. 908–920, November 2005.
[4] S. Bobba, T. Thorp, K. Aingaran, and D. Liu, “IC power distribution challenges,” in Proc. Intl. Conf. Computer Aided Design, pp. 643–650, 2001.
[5] J. Kim et al., “Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission,” in Proc. Electronic Components and Technology, pp. 610–614, 1998.
[6] D. Pandini and G. A. Repetto, “Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design,” in Proc. PATMOS, pp. 532–542, 2006.
[7] M. Hansson, B. Mesgarzadeh, and A. Alvandpour, “1.56 GHz on-chip resonant clocking in 130nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 241–244, 2006.
[8] B. Mesgarzadeh, M. Hansson, and A. Alvandpour, “Jitter characteristic in charge recovery resonant clock distribution,” IEEE J. Solid-State Circuits, vol. 42, pp. 1618–1625, July 2007.
[9] B. Mesgarzadeh, M. Hansson, and A. Alvandpour, “Low-Power Bufferless Resonant Clock Distribution Networks”, in Proc. 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 960-963, 2007.
[10] S. Naffziger, B. Stackhouse, and T. Grutkowski, “The Implementation of a 2-core Multi-Threaded Itanium®-Family Processor”, in IEEE International Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 182-183, 2005.
[11] C. J. Anderson et al., “Physical Design of a Fourth-Generation POWER GHz Microprocessor”, in IEEE International Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 232-233, 2001.
[12] B. Mesgarzadeh, C. Svensson, and A. Alvandpour, “A New Mesochronous Clocking Scheme for Synchronization in SoC”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 6, pp. 605-608, 2004.
[13] S. Chan et al., “A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor”, in IEEE International Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 512-513, 2008.
